1. The Field of the Invention
The present invention relates generally to systems and devices for high speed data transmission. More particularly, embodiments of the present invention concern systems and devices having shared functionality to efficiently process multiple data signals from a host such as a MAC device, framer or FEC processor.
2. The Relevant Technology
Computing and networking technology have transformed our world. As the amount of information communicated over networks has increased, high speed transmission has become ever more critical. Many high speed data transmission networks rely on optical transceivers and similar devices for facilitating transmission and reception of digital data embodied in the form of optical signals over optical fibers. Optical networks are thus found in a wide variety of high speed applications ranging from as modest as a small Local Area Network (LAN) to as grandiose as the backbone of the Internet.
Typically, data transmission in such networks is implemented by way of an optical transmitter (referred to as an electro-optical transducer), such as a laser or Light Emitting Diode (LED). The electro-optical transducer emits light when current is passed through it, the intensity of the emitted light being a function of the current magnitude. Data reception is generally implemented by way of an optical receiver (referred to as an opto-electrical transducer), an example of which is a photodiode. The opto-electrical transducer receives light and generates a current, the magnitude of the generated current being a function of the intensity of the received light. The electro-optical transducer and the opto-electrical transducer are often integrated into a single optoelectronic device, such as an optical transceiver.
Many optoelectronic device architectures use a higher signaling rate to send optical signals over an optical fiber than to receive electrical signals from a line card on which they are used. This requires the device to convert from the higher optical data rate to the lower electrical data rate, and vice versa. Examples of such devices are those that comply with the 300-pin MSA or XENPAK form factor standard. The IC component that performs this function is called a serializer/deserializer, also commonly referred to as a SerDes.
The serializer portion of the SerDes receives two or more parallel data signals from a line card at a first signal rate and provides as output one or more serial data signals at a second signal rate. The number of output serial data signals is usually less than the number of input parallel data signals, although the same amount of data is conveyed by the output serial data signals. Consequently, the signal rate of one of the parallel data signals is less than the signal rate of one of the serial data signals. To accomplish this conversion, the serializer contains a clock and data recovery (“CDR”) and/or delay lock loop (“DLL”) function on each input data lane to receive the data from the line card. The serializer frequently contains a clock multiplier unit (“CMU”) to synthesize the high rate clock required for the serial data signal rate and a multiplexer with ratio M:1, corresponding to M input parallel data lanes that are multiplexed onto one output serial signal. Note that when the serializer serializes M input parallel data signals onto one output serial data signal, the parallel data signal rate is 1/M of the serial data signal rate. Of course, the M input parallel data lanes may also be multiplexed onto X output serial data lanes, where X is less than M, in which case the parallel data signal rate is X/M of the serial data signal rate. As used herein, “single-channel serializer” may be used to refer to a serializer that multiplexes multiple signals into a single signal and “multi-channel serializer” may be used to refer to a serializer that multiplexes multiple signals into a fewer number of signals not less than two signals.
The deserializer portion of the SerDes performs a function that is the reverse of the function performed by the serializer. It has an input CDR that recovers the serial data stream clock, and can have an input flip-flop into which the serial data is clocked into. There is then a 1:M (or X:M) demultiplexer which demultiplexes the single (or X) serial data stream(s) into M electrical data streams. A “single-channel deserializer” refers to a deserializer that demultiplexes a single input signal into multiple signals and usually has a single CDR, while a “multi-channel deserializer” refers to a deserializer that demultiplexes multiple input signals into a greater number of signals and usually has a plurality of CDRs, the number of CDRs corresponding to the number of input signals. Note that the designations “single-channel” and “multi-channel” may also be applied to a SerDes when the SerDes can convert between multiple signals and a single signal or multiple signals and a fewer number of signals, respectively.
Other optoelectronic device architectures use the same signaling rate to send optical signals over an optical fiber and to receive electrical signals from a line card, and as a result do not require a SerDes to convert between a high optical data rate and a low electrical data rate. For example, the XFI interface standard is used with the XFP form factor standard. It has a single 10 G electrical data stream which is mapped to a single 10 G optical data stream. Such devices can be implemented with a single CDR in the electrical to optical direction and a single CDR in the optical to electrical direction.
As demands for higher data transmission speeds between points in optical networks have increased, single-channel and multi-channel device architectures have been proposed and/or developed which include one higher-speed optical channel or multiple lower-speed optical channels having a relatively high aggregate speed. When the optical per channel data rate is different than the electrical per channel data rate, these device architectures require either a multi-channel or single-channel SerDes depending on the number of optical channels and other factors. Additionally, multi-channel device architectures may require multiple SerDes, whether single-channel or multi-channel. When the optical per channel data rate is the same as the electrical per channel data rate, these device architectures require either a multi-channel or single-channel CDR function, also depending on the number of optical channels. As used herein, a multi-channel CDR or CDR function refers to a CDR which can recover the clock and data for a plurality of data channels and provide the same number of recovered data channels. In contrast, a single-channel CDR or CDR function refers to a CDR which can recover the clock and data for a single data channel and provide a single recovered data channel.
The conventional approach to implementing multiple serializers, whether single-channel or multi-channel, would be to replicate the standard serializer architecture described above N times (e.g., once for every one of N optical channels), and would cost N times the silicon area. Similarly, the conventional approach to implementing a multi-channel CDR would be to replicate the standard CDR architecture N times and would cost N times the silicon area.